On June 18, according to the Korea Economic Daily, Samsung Electronics will launch SAINT-D technology within this year, which can integrate HBM memory with processor chips in 3D.
SAINT-D is a 3DIC advanced packaging technology of Samsung Electronics, which aims to vertically integrate logic die and DRAM memory die. The specific implementation of this technology is reported to be establishing a silicon interposer between the processor and the HBM chip.
Samsung Electronics recently stated at the Samsung Foundry Forum 2024 North America that its SAINT-D technology is currently in the proof-of-concept stage.
South Korean media said that SAINT-D technology has taken the AI semiconductor field a step further:
Currently, HBM memory and processors are connected by 2.5D packaging, and there is a certain distance between the two, which not only introduces greater transmission delays, but also affects the quality of electrical signals and increases data movement power consumption. SAINT-D technology reduces the distance between processors and HBM memory to a lower level, which is conducive to further unleashing the performance potential of AI accelerator chips.
For Samsung Electronics as a whole, the application of SAINT-D can also drive the development of HBM and foundry business, as it can provide full-process "turnkey" services from advanced node foundry, HBM memory production to overall packaging integration.
According to data from market research firm MGI, the scale of the advanced packaging market such as SAINT-D will grow from US$34.5 billion in 2023 to US$80 billion.
