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5G-ready jitter attenuators enhances system reliability and performance

Technology Cover
Nach Datum: 2019-06-30, Silicon Labs

Silicon Labs has extended its family of Si539x jitter attenuators with new device options providing a fully integrated reference, improving system reliability and performance while simplifying PCB layout in high-speed networking designs. The new jitter attenuators are purpose-built to meet the critical reference clock demands of 100/200/400/600/800G designs, offering more than 40% margin to the stringent jitter requirements of 56G PAM-4 SerDes employed in state-of-the-art Ethernet switch SoCs, PHYs, FPGAs and ASICs while affording a solution that is future-proofed for emerging 112G SerDes designs.

“Network equipment providers are racing to develop higher speed, higher capacity gear capable of handling 5G wireless traffic. This transition is driving the need for higher performance timing solutions for fronthaul/backhaul, metro/core and data centre applications,” said James Wilson, general manager of timing products at Silicon Labs. “FPGAs and PHYs with integrated 56 Gbps SerDes enable higher capacity 100/200/400/600/800G optical and Ethernet line cards but face increasingly complex circuit board design and layout challenges. By integrating the reference inside Silicon Labs’ latest Si539x jitter attenuators, we are helping to ease the industry migration to higher port count, higher capacity 100/200/400/600/800G designs.”

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